Japanese Patent Application No. 2000-046389, filed Feb. 23, 2000, is hereby incorporated by reference in its entirety.
1. Technical Field
The present invention relates to methods for making semiconductor devices, and particularly to methods for making semiconductor devices including those having a silicon-on-insulator (SOI) structure.
2. Related Art
In general, in a known semiconductor device having a silicon-on-insulator (SOI) structure, a delimited region is formed into a single-crystal silicon layer which is provided over a semiconductor substrate with an insulating layer therebetween to delimit the single-crystal silicon layer into a plurality of segments, and the delimited single-crystal silicon layer segments are activated to provide semiconductor integrated-circuit elements. Such a semiconductor device has been produced by various methods.
FIG. 4 includes process drawings showing an embodiment of a conventional method for making an SOI-structured semiconductor device. The semiconductor device is enlarged in the drawing.
This conventional method for making the semiconductor device includes a delimiting step 110 for delimiting a silicon layer provided over a semiconductor substrate with an insulating layer therebetween, and an implantation step 120 for implanting a dopant into the delimited silicon-layer segments to activate the delimited silicon-layer segments.
In more detail, this delimiting step 110, as shown in FIG. 4(a), prepares an SOI substrate 100 in which a single-crystal silicon layer (silicon layer) 113 is provided over a single-crystal silicon substrate 111 with an insulating layer 112 composed of silicon dioxide (SiO2) therebetween. Next, a protective film 114 composed of silicon nitride (Si3N4) is provided on a position corresponding to each active region of the single-crystal silicon layer 113 (see FIG. 4(b)). The SOI substrate 100 provided with the protective film 114 is heated in an oxidizing atmosphere to partially oxidize the single-crystal silicon layer 113 to convert the single-crystal silicon layer 113 into a plurality of isolated single-crystal silicon-layers 113a which are delimited by an insulating layer 115 as a delimited region, and then the protective film 114 is removed (FIG. 4(c)). Hereinafter, the insulating layer 115 and the insulating layer 112 are collectively referred to as an insulating layer 116.
The implantation step 120 will now be described. In this implantation step 120, as shown in FIG. 4(d), a region of the SOI substrate 100 in which the dopant will not be implanted is covered and a resist 117 is formed by a photolithographic process. For example, when n-channel MOS transistors (nMOSs) are formed in the single-crystal-silicon-layer segments 113a shown in FIG. 4, portions for forming p-channel MOS transistors (pMOSs) are covered and the resist 117 is provided. When, for example, nMOSs are formed in the single-crystal-silicon-layer segments 113a shown in FIG. 4, the entire surface of the SOI substrate 100 is irradiated with dopant ions 119, for example, boron (B) or boron difluoride (BF2) ions (see FIG. 4(d)) to implant dopant ions 119 into the single-crystal-silicon-layer segments 113a via a thin insulating layer (a sacrificial oxide layer) not shown in the drawing. The implantation of the dopant ions 119 is performed by an implantation energy which is set so that the position of the maximum of the implanted dopant concentration distribution lies within the region of each single-crystal-silicon-layer segment 113a. The single-crystal-silicon-layer segment 113a is thereby activated as a p-type semiconductor layer 118. As shown in FIG. 4(e), the resist 117 is removed.
Subsequent to the implantation step 120, a gate electrode, a source electrode, and a drain electrode are provided over the p-type semiconductor layer 118 with an insulating layer therebetween by a known process.
FIG. 5 is a plan view of an embodiment of a semiconductor circuit element having electrodes provided by the above known process. FIG. 6 is a cross-sectional view taken from line VIxe2x80x94VI in FIG. 5, and FIG. 7 is a cross-sectional view taken from line VIIxe2x80x94VII in FIG. 5. Also in these drawings, the device is enlarged.
In these drawings, a gate electrode 132 is formed over the p-type semiconductor layer 118 of the SOI substrate 100 separated by an insulating layer (gate insulating film) 131. A source region and a drain region (both not shown in the drawing) doped with an n-type dopant such as phosphorus are formed at both sides of the gate electrode 132 of the p-type semiconductor layer 118, and a source electrode 133 and a drain electrode 134 beside the gate electrode 132 are provided on the source electrode and the drain electrode, respectively, to complete a semiconductor circuit element (nMOS) 130.
3. Problems With the Related Art
When the single-crystal silicon layer 113 is partially oxidized by the above-mentioned so-called local oxidation of silicon (LOCOS) to delimit the single-crystal silicon layer 113 into a plurality of single-crystal-silicon-layer segments 113a, oxidation propagates up to a portion under the protective film 114 to form a bird""s beak and single-crystal silicon having a wedge shape remains under the bird""s beak. When the single-crystal-silicon-layer segment 113a is doped with the dopant for activation, the dopant is implanted by an implantation energy which is set so that the maximum (peak) position of the dopant concentration distribution lies within the single-crystal-silicon-layer segment 113a covered with a thin insulating layer (for example, a sacrificial oxide film). Thus, as shown in FIG. 7, bottom edges Ea and Eb of the p-type semiconductor layer 118 are covered by the thick insulating layer 116 and the dopant concentrations in these edges are significantly lower than the dopant concentrations in other portions (for example, the center of the semiconductor layer 118) of the semiconductor layer 118. This phenomenon also occurs when the dopant is implanted without use of the sacrificial oxide film or the like.
Thus, a parasitic device is formed between these edges Ea and Eb and the gate electrode 132, and between these edges Ea and Eb and other electrodes 133 and 134. As a result of the formation of the parasitic device, as shown in FIG. 8, a semiconductor circuit element 150 is regarded as a serial connection of an original circuit element 151 and a circuit element 152 as the parasitic device. Thus, the characteristic curve of the drain current (ID) verses the gate voltage (VG), as shown in FIG. 9, corresponds to a combination of the characteristic curve J of the original semiconductor circuit element 151 and the characteristic curve K of the parasitic device, creating some problems such as leakage currents.
In order to solve such a problem, in conventional methods, ions are reimplanted into the edges Ea and Eb to increase the concentration of the dopant at the edges Ea and Eb. Accordingly, the number of the production steps and production costs are increased.
When no dopant is implanted, the shapes of the electrodes must be modified or connecting holes must be provided in the semiconductor layer so as to form no parasitic device. These countermeasures also cause an increase in the number of production steps.
Embodiments include a method for making an SOI-structured semiconductor device. The method includes delimiting step for forming a delimited region in a silicon layer provided over a semiconductor substrate with an insulating layer therebetween to delimit the silicon layer into a plurality of delimited silicon-layer segments. The method also includes an implantation step for implanting a dopant into the delimited silicon-layer segments to activate the silicon layer. The implantation step includes implanting a dopant with an implantation energy which is set so that a maximum of the dopant concentration distribution lies at or adjacent to a peripheral portion of each of the delimited silicon-layer segments.
Embodiments also include a method for fabricating a semiconductor device having a silicon-on-insulator structure. The method includes forming a plurality of delimited silicon-layer segments having end portions in a silicon layer, and implanting a dopant into the delimited silicon-layer segments to activate the silicon layer, wherein the implanting is carried out so that a maximum dopant concentration lies in the end portions of each of the delimited silicon-layer segments.